The present invention relates generally to integrated circuits and methods of making the same. More particularly, an anisotropic electrically conductive layer is used to couple a die to traces and/or package contacts.
A reduced-scale integrated circuit assembly is frequently referred to as chip scale package (CSP), since the size of the package is about the size of the integrated circuit chip or die incorporated in the package.
There are a wide variety of integrated circuit packages that are currently available. By way of example, referring to FIG. 1, a typical Ball Grid Array (BGA) integrated circuit package generally indicated by the reference numeral 10 is shown. BGA package 10 includes a dielectric substrate 12, an integrated circuit die 14, an array of bonding wires 16, an encapsulating material 18, and an array of contacts or solder balls 20.
Substrate 12 is made from a rigid material capable of supporting the other components of the package during the assembly of the package. Integrated circuit die 14 includes a plurality of electrically conductive input/output terminals on its top surface. Substrate 12 includes a plurality of electrically conductive terminals on its top surface. Each of the bonding wires 16 electrically connects a respective one of the input/output terminals on the top surface of integrated circuit die 14 to a respective one of the terminals on the top surface of substrate 12. Substrate 12 further includes a plurality of electrically conductive contact terminal pads on its bottom surface, and a plurality of electrically conductive traces (not shown), each of which electrically connects a respective terminal on the top surface of substrate 12 to a respective contact terminal pad on the bottom surface of the substrate 12. Encapsulating material 18 encapsulates integrated circuit die 14, at least the top surface of substrate 12, and bonding wires 16. Contacts or solder balls 20 are attached to associated contact terminal pads on the bottom surface of substrate 12, thereby allowing external electrical elements to be electrically connected to integrated circuit die 14.
In the field of integrated circuits, attempts are continuously being made to reduce the size of the integrated circuit die and to simultaneously increase the number of circuits provided on the die. More sophisticated and smaller integrated circuit dies are advantageous since, by being smaller, they are more easily incorporated into devices which are able to perform more complex tasks due to the advanced sophistication of the dies. However, the advantages obtained by decreasing the size of the die may be partially or wholly lost if the package or assembly which incorporates the die is excessively large or cumbersome. The conventional BGA package of FIG. 1 for example has packaging dimensions, i.e. the dimensions of the substrate 12 and encapsulating material 18, which are much larger than the dimensions of the integrated circuit die 14.
Furthermore, the pitch between the input/output terminals on the top surface of the IC die of the BGA package of FIG. 1 presently may not decrease below about 85-90 micron (.mu.m) due to space constraints inherent with use of the bonding wires for electrically connecting the IC die input/output terminals to the substrate terminals. Accordingly, the density of input/output terminals on a given surface area of the IC die may not increase above a certain number in order to maintain the I/O terminal pitch at or above 85-90 micron (.mu.m), which limits the degree of complexity of the IC die obtainable for a given die size.
Another type of currently available integrated circuit package employs a so-called flip-chip IC die. This die has been subjected to a wafer level process which includes connecting metallic bumps to the surface of the die, and reflowing the bumps in order to "redistribute" the I/O terminals on the surface of the die. The die is then turned over (hence the term flip-chip) so that the surface with the reflown bumps faces down to be connected directly with terminals on a PC board. Although the flip-chip IC package tends to be smaller in size than the previously described BGA package, the minimum I/O terminal pitch currently available while maintaining adequate electrical connection using the reflown bumps of the flip-chip die is about 200-250 microns (.mu.m).
In view of the limitations of the currently available packaging, an improved arrangement for electrically coupling a die to associated contacts or leads would be desirable.